前苏联专利SU1314967A3 Generator with automatic phse control

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专利摘要:
An automatic phase-controlled oscillator circuit for producing an output clocking signal whose phase and frequency vary with those of an input information signal applied thereto comprises an input circuit for receiving the input information signal; a variable-frequency tuning circuit for receiving a control signal and coupled to the input circuit for tuning on the basis of the frequency of the control signal to pass the information signal as a tuned signal; and a clocking signal generator, such as a phase-locked loop circuit, for providing the output clocking signal in dependence upon the phase of the tuned signal. The invention is favorably applied to a digital video tape recorder (DVTR) wherein the information signal is a digital signal reproduced from a tape as a result of relative motion between the tape and the DVTR, and the control signal is also reproduced from the tape to represent such relative motion. The oscillator circuit also preferably includes a phase comparator providing an error signal representing the phase difference as between the input information signal and the output clocking signal, and a phase adjuster, such as a variable delay line, responsive to the error signal.
公开号:SU1314967A3
申请号:SU803210746
申请日:1980-10-30
公开日:1987-05-30
发明作者:Мария Риусуке；Фудзимори Ясухиро
申请人:Сони Корпорейшн (Фирма)；
IPC主号:

专利说明:

This invention relates to synchronization and is intended to generate synchronization pulses synchronized with a varying frequency of a reproduced or received digital signal.
The purpose of the invention is to improve the synchronization stability.
The drawing shows a structurally functional electric generator circuit with automatic phase adjustment.
Generator with automatic phase adjustment contains differentiating circuit 1, full-wave rectifier 2, frequency-controlled bandpass filter 3, second frequency divider 4, adjustable delay line 5, keystone generator 6, first phase comparator 7, low-pass filter 8, adder 9 , a control signal source 10, a voltage controlled generator 11, a first frequency divider 12, a second phase comparator 13, a switch 14 with three steady states, a charging current generator 15, a current generator 16 , A charging capacitor 17 and an optional lowpass filter 18.
The generator with automatic phase adjustment works as follows.
The output signal is the output voltage of the voltage controlled oscillator 11, the frequency and phase of which are phase locked with the frequency of the signal using a phase locked loop, including the first frequency divider 12, the first phase comparator 7, the low-pass filter B and the adder 9. In this case, the circuit consisting of the second phase comparator 13, switch 14, charge current and discharge current generators 15 and 16, respectively, charge capacitor 17, additional low pass filter 18 and adjustable delay line 5, yn Aulus a phase of a reference signal by comparing the phase voltage on the input information, representing a tsif-
Thus, an increase of
An binary binary signal, with a voltage phase controlled by a voltage, generates synchronization stability. The rapper 11, and the subsequent generation of the Source 10 controlling the signal controlling the voltage by the static link formed by the switch 14, current generators 15 and 16, and the charge can be implemented as a frequency discriminator of the pulse frequency. In this case, his input
15
20
25
1WM capacitor 17 with its subsequent filtering by an additional low-pass filter 18 and using the generated voltage to control the delay of the reference voltage in the adjustable delay line 5.
The reference signal is generated from the voltage at the information input by differentiating the input digital binary signal, as a result of which bipolar pulses are produced, corresponding to the fronts of the digital binary signal, two-wavelength rectification of the bipolar pulses produced in two-wavelength rectifier 2, filtering one-field ph1) 1x pulses of a frequency-controlled band-pass filter 3, as a result of which a voltage is generated at its output, the frequency of which corresponds to the clock frequency digital binary signal, and frequency division by the second divider 4 frequencies, the division factor of which is equal to the division factor of the first frequency divider 12, which ensures the equality of the frequency of the output voltage of the generator 11 to the clock frequency of the output digital binary signal.
When the frequency of the input digital binary signal changes in frequency, the voltage of the control signal source 10 automatically changes. This ensures that the band-pass filter 3 controlled at the frequency is tuned to the clock frequency of the input digital binary signal, produces the reference signal and, in addition, by applying this voltage to the adder 9 pre-adjusts the phase-locked loop to the frequency 45 of the reference signal. After completion of the phase-locked loop tuning, additional phase-matching of the PAL loop is performed along a circuit including a second phase comparator 13, followed by another 30
40
50
lami integration and filtering, as well as an adjustable delay line 5.
Thus, an increase in synchronization stability is achieved. Source 10 control signal
stability of synchronization. Source 10 control signal
can be made in the form of a frequency discriminator of the pulse frequency. In this case, his input
must be connected to a source of pulses whose frequency corresponds to or is proportional to the clock frequency of the pulses at the information input.

权利要求:
Claims (1)
[1]
Invention Formula
Generator with automatic phase adjustment, containing the first phase comparator, a low-pass filter, an adder, the second input of which is connected to the control signal source, a voltage-controlled generator, the first frequency divider connected to the second input of the first phase comparator , characterized in that, in order to increase the synchronization stability, a series-connected differential circuit is introduced into it, the input
Editor A.Dolinich
Compiled by S. Daniel N. Techred N. Glushenko
Order 2225/59
Circulation 902 Subscription
VNIIPI USSR State Committee
for inventions and discoveries 113035, Moscow, Zh-35, Raushsk iab., d. 4/5
-Production and printing company, Uzhgorod, st. Project, 4
which is a device information input, a full-wave rectifier, a frequency-controlled band-pass filter, the control input of which is connected to a control signal source, a second frequency divider, an adjustable delay line and a trapezoidal shaper, and a second phase comparator, whose inputs are connected respectively to the information input of the device and the output of a voltage controlled generator, a switch with three stable states, the first input of which is connected to the gene ator current charge, to a second input - the discharge current generator, and across the output - a charging capacitor, and an optional lowpass filter connected between the output switch and the control input of the variable delay line.
Proof-reader I.Erdeyi

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同族专利:

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引用文献:

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US3609408A|1969-09-30|1971-09-28|Rca Corp|Clock pulse generator|

US3657661A|1970-06-16|1972-04-18|Itt|Fm demodulator system|

US3753143A|1971-08-05|1973-08-14|Honeywell Inf Systems|Phase locked oscillator for integer pulse rates|

US3792473A|1972-11-21|1974-02-12|Bendix Corp|Vor receiver with adaptive filters and phase shifter for improved accuracy|

JPS516515A|1974-07-05|1976-01-20|Hitachi Ltd|

US3908115A|1974-10-07|1975-09-23|Weston Instruments Inc|Adaptively tuned data receiver|

US4156855A|1978-01-26|1979-05-29|Rca Corporation|Phase-locked loop with variable gain and bandwidth|

FR2437733B1|1978-08-30|1981-11-06|Cit Alcatel|GB2129634B|1980-03-10|1984-10-31|Control Data Corp|A self-adjusting delay device|

JPH0436519B2|1984-06-08|1992-06-16|Matsushita Electric Ind Co Ltd|

US4811128A|1986-02-14|1989-03-07|Victor Company Of Japan|Digital signal recording and reproducing apparatus having rotary magnetic heads|

JPS62164651U|1986-04-07|1987-10-19|

NL8801844A|1988-07-21|1990-02-16|Philips Nv|STARTING THE TIMING IN A DEVICE FOR DERIVING A CLOCK SIGNAL.|

US4875108A|1988-08-02|1989-10-17|Magnetic Peripherals Inc.|Phase lock loop|

US5119043A|1990-06-27|1992-06-02|Digital Equipment Corporation|Auto-centered phase-locked loop|

US5036293A|1990-10-19|1991-07-30|Rca Licensing Corporation|Oscillator for use with video signal time scaling apparatus|

US5307212A|1991-08-22|1994-04-26|Rohm Co., Ltd.|Trapezoidal wave generation in a video control signal write circuit|

KR970003810B1|1993-04-14|1997-03-22|삼성전자 주식회사|Nonvolatile semiconductor integrated circuit having address transition detector circuit|

JP2616701B2|1994-06-29|1997-06-04|日本電気株式会社|High-speed pull-in control circuit for clock-dependent synchronizer.|

US5943379A|1997-06-11|1999-08-24|National Semiconductor Corporation|Multi-phase trapezoidal wave synthesizer used in phase-to-frequency converter|

US6014417A|1997-06-11|2000-01-11|National Semiconductor Corporation|On-chip phase step generator for a digital phase locked loop|

JP3879951B2|1997-09-02|2007-02-14|ソニー株式会社|Phase adjusting device, phase adjusting method and display device|

US7856224B2|2005-03-31|2010-12-21|General Electric Company|Systems and methods for recovering a signal of interest from a complex signal|

US7869499B2|2007-07-27|2011-01-11|Fsp Technology Inc.|Variable-frequency circuit with a compensation mechanism|

US9264052B1|2015-01-20|2016-02-16|International Business Machines Corporation|Implementing dynamic phase error correction method and circuit for phase locked loop |

US9853807B2|2016-04-21|2017-12-26|Taiwan Semiconductor Manufacturing Co., Ltd.|Automatic detection of change in PLL locking trend|

法律状态:

优先权:

申请号 | 申请日 | 专利标题

JP54141671A|JPS6247375B2|1979-10-31|1979-10-31|

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